The invention relates to information processors and more particularly to information processors having a write buffer circuit for temporarily storing data and addresses which are thereafter to be stored in a main memory of the processor, and for writing, storing and reading the data with respect to their addresses.
An information processor of a computer system, for example, often uses a cache memory to speed an access to a main memory. A cache memory is a local, high-speed memory that can rapidly take in data which is thereafter stored in a main memory. That is, a value which is obtained by a first access to the main memory is stored in the cache memory. A second and subsequent access function is performed, not to the main memory, but to the cache memory because it enjoys the benefits of localism, both in space and in time, and because there is a need for enough time to carry out a program execution for giving data access to the main memory.
A cache memory has a write-through system which is one of its control systems. An information processor employing the write-through system first gains a write access to a main memory whenever data is written into the cache memory. This system is adequate for maintaining a consistency of the data stored in the main memory and the cache memory. However, the write access to the main memory may require several times as long as a write access to the cache memory. When the ratio of the stored program instructions increases, there is a competition between the main memory and peripheral I/O devices for gaining access to a data bus, etc., thus degrading overall system performance.